For trench DRAM cells, one serious drawback is the parasitic sidewall leakage through the trench sidewalls. This is due to the formation of a parasitic sidewall transistor as explained in a paper by N.C.C. Lu et al., IEEE J. Solid-State Circuits SC-21:627 (1986). The parasitic MOS transistor causes a leakage current to pass through a sidewall portion of a channel formed adjacent to the trench. Such leakage can occur from bitline contact to the storage node, and from storage node to the substrate, for example. One way to reduce this parasitic sidewall leakage is to increase the thickness of the oxide collar normally placed around the trench near the top of the trench (the trench neck). However, collar thickness is increased at the expense of storage node thickness within the trench, the size of the trench opening being fixed. Thus, increasing the collar thickness (1) reduces the contact area available for contact with the storage node, (2) increases the RC time constant of the storage node poly, and (3) introduces other process constraints.
Minimizing the leakage of stored charge to preserve the stored information is important to the functional operation of dynamic memory (DRAM). For most trench DRAM cells, this means reducing the parasitic sidewall leakage to the lowest levels, without affecting other cell characteristics. Increasing the collar thickness alone is not a viable alternative, especially with increasing memory cell density when memory cells are scaled down. It is therefore desirable to find alternative ways to reduce trench sidewall leakage which do not have these drawbacks associated with increased collar thickness.